As manufacturing processes descend below 90 nm geometries, the well proven yield management system tools begin to lose effectiveness. In part, visibility of particulate defects is near the limit of optical inspection tools. Current yield management system tools discern correlations in areas of die which diverge from standard images. These tools cannot currently exploit understanding of the circuit functionality to geometrically locate divergences. There are also design-introduced electrical faults that are yield limiting at these tighter geometries which are detectable in the production test environment.
To improve the testability of high density semiconductor devices, modern design practice inserts additional circuitry specific to test such as scan chains. A scan chain in test mode is configured to be a very long shift register. Patterns generated to operate with scan chains do not have any functional utility and purely observe or control potential electrical defects. But scan chain and bit have little relationship to geometrical location of the defects.
Scan Basics
To explain the new process, it is first necessary to provide some background on established techniques of SCAN in semiconductor test. The approach of scan methodology is to replace all flip-flops in a design with scan flip-flops. Scan flip-flops provide two paths into each flip-flop: one for the mission of the design, and a second to facilitate test.
Scan Flip-Flops—There are two most common methods of implementation today:
MUXD—This scan flip-flop approach places a mux on the front end of the D-input. The selector to the mux, known as the scan enable, determines whether to use the mission mode input or the scan test input.
LSSD—Another common scan flip-flop approach is to use two clocks. One clock latches the mission path input into the flip-flop while the second clock latches the scan test input data into the flip-flop.
Scan Chains—By stitching all of the scan flip-flops, or scan cells, together into one or more scan chains, each flip-flop can be preset or observed. This allows for test patterns to be constructed that will concentrate on finding faults in mini sub-circuits. The first illustration FIG. 1 shows the circuit prior to scan insertion, and the second FIG. 2 shows the circuit after a MUXD scan insertion.
In FIG. 2, notice that each flip-flop has two input paths as controlled by a mux on the input. When the scan enable “SE” is asserted, the scan chain operates as a shift register. This allows for each flip-flop to be set to a specific state. It also allows for the observation of each flip-flop state as the values are shifted out of the device onto the scan output “SO”. Each flip-flop, or scan cell is numbered for the purpose of referencing.
For this example, the ‘and’ gate can be tested by shifting data into scan cells 3 and 2. After the desired test condition has been loaded, the scan enable is de-asserted and a clock can be applied to capture the output of the combinational logic as observed at scan cell 1. The scan enable is once more applied and the result data as captured at scan cell 1 is shifted through the scan chain until it arrives on the device output for the scan chain.
Functional Tester Background
Historically, testers apply a set of simulated stimulus, and validate that the response on the device outputs match the results expected from the simulation. Functional testers are designed to report in a go/no-go fashion that all of the outputs matched the expected results for all checked strobe points or not. Functional testers are not architected to understand design criteria of the device under test such as the scan structures. Thus, while functional testers can understand which output signals contained failures, each output signal can represent tens of thousands of internal scan cells.
Another form of semiconductor testing uses optical scanning of wafers and comparison of the resultant images to identify variances from normal. These variances are reported as bounding boxes containing the geometric features that are found in some but not all wafer images. Yield management systems conduct pareto analysis to determine which defects have the greatest impact on yield and prioritize failure analysis. As processes approach and surpass 90 nanometer in feature size, optical scanning becomes less acute.
Thus it can be appreciated that what is needed is a capability to translate a scan cell pattern production test failure to an area on a wafer containing a fault.